Silicon-On-Insulator (SOI) technologies have advanced dramatically in recent years towards the goal of producing thin single-crystal silicon films on insulating substrates. See, for example, G. Possin et al., "MOSFET's Fabricated in Laser-Recrystallized Silicon on Quartz Using Selectively Absorbing Dielectric Layers," IEEE Trans. Electron Devices, Vol. ED-31, pp. 68-74 (1984); S. Malhi et al., "Characteristics of MOSFETs Fabricated in SPE Grown Polysilicon," 1985 Sympos. on VLSI Technol., Digest of Tech. Papers, ; pp. 36-37 (Tokyo, 1985); Y. Kobayashi et al., "MOSFET Characteristics of Connected Silicon Islands on Fused Silica," Extended Abs. 16th Conference on Solid-State Devices and Materials, pp. 623-626 (Kobe, Japan, 1984). As suggested by the foregoing articles, the term "SOI" has been most commonly used in connection with metal oxide semiconductor field effect transistors (MOSFETs). As is discussed further below, existing SOI technologies suffer from material limitations in the quality of the crystalline material produced, such as grain boundaries, crystal defects, and doping constraints. Accordingly, transistors and other devices fabricated therefrom are inferior in many areas of performance to devices made using a conventional bulk silicon wafer process. Also, existing SOI technologies do not permit practical BJTs to be fabricated on glass, for reasons further discussed below.
Transistors fabricated in SOI films appear very attractive for a number of applications. The important feature in the SOI structure is the insulating substrate that reduces or eliminates certain parasitic device elements that are present in bulk silicon devices. These parasitic device elements include collector substrate capacitance and collector-substrate leakage current, which can both decrease circuit speed in bipolar devices. Parasitic device elements in CMOS monolithic silicon integrated circuits can also cause undesirable field conduction and a very undesirable phenomenon known as latch-up. In addition, there are many other parasitic capacitances and conductances in conventional monolithic silicon MOS circuits that decrease circuit speed. SOI transistors eliminate or reduce many of these parasitic device elements, allowing potentially faster integrated circuits to be fabricated in a smaller area.
SOI devices are also attractive as candidates for high voltage applications. In the design of these devices, the parasitic electrical elements and substrate connections in a bulk silicon integrated circuit become a limiting factor. The SOI device has no such parasitic elements because the substrate is an insulator. Thus, SOI technology will allow the fabrication of high voltage devices in a much smaller area, due to the reduced isolation area necessary, and they should be able to operate at higher voltages than devices made with bulk silicon technology.
In addition to the potential for reduced parasitic capacitance and leakage current, SOI devices have improved radiation hardness due to reduced junction area. SOI transistors on glass substrates are particularly attractive for sensors and displays, where high thermal, electrical, and physical isolation, an optically-transparent substrate, and compatibility with large areas are frequently important. For example, a high-performance transistor process for an active-matrix liquid-crystal display would allow the integration of the active pixel matrix with peripheral circuits on the same substrate, reducing electrical connections significantly, as discussed in A. Lakatos, "Promise and Challenge of Thin-film Silicon Approaches to Active Matrices," 1982 International IEEE Display Res. Conference, pp. 146-151 (New York, 1982).
A wide variety of techniques have been proposed for realizing thin silicon films compatible with high-performance devices on an insulating substrate such as glass or oxidized silicon wafers. Crystallization of deposited polysilicon films using thermal energy derived from incident beams has met with some success. See, for example, R. Lemons et al., "Laser Crystallization of Si Films on Glass," , Appl. Phys. Letters, Vol. 40, pp. 469-471 (1982). However, performance of such devices employing recrystallized silicon is still limited by problems associated with silicon crystal quality. Moreover, these technologies are often limited in that the thickness of the SOI semiconductor layer which can be deposited on glass is on the order of one micron or less. Thus, those conventional bulk silicon devices requiring single-crystal layers thicker than about one micron often cannot be fabricated in SOI form. Device properties in polysilicon or in amorphous silicon films are generally still less favorable. Field-effect mobilities in unrecrystallized polysilicon transistors are limited to less than 50 cm.sup.2 /V-sec, while amorphous material usually produces channel mobilities on the order of 1 cm.sup.2 /V-sec. An interesting process for producing single-crystal silicon films on silicon dioxide on silicon has been presented recently in J. Lasky et al., "Silicon-on-Insulator (SOI) by Bonding and Etch-Back," Digest 1985 IEEE Int. Electron Devices Mtg.; pp. 684-687 (Dec. 1985). The reported process involves bonding two oxidized wafers together at high temperature and then thinning one wafer to produce a silicon-on-oxide film. However, this process does not yield the desirable properties of a glass substrate for sensor/display applications, and rather large voids during the bonding process are a concern. Work of a similar nature using electrostatically-produced bonds is reported in B. Anthony, "Dielectric Isolation of Silicon by Anodic Bonding," Journal Of Applied Physics (USA), Vol 58, No. 3, pp. 1240-1247 (Aug. 1985); R. Frye et al., "A Field-Assisted Bonding Process for Silicon Dielectric Isolation," Journal of Electrochemical Society (USA), Vol. 133, No. 8, pp. 1673-1677 (Aug. 1986).
Sensors have used glass substrates for many applications ranging from pressure transducers and micromachined chromatographs, where enclosed volumes are desired, to infrared imagers where thermal and/or electrical isolation of devices is required. Often these "glass substrate" sensors and utilize on-chip circuitry for signal processing, multiplexing and interfacing with other electronic circuits. With presently available technology, the circuits would have to be built into the silicon or attached to the glass substrate in a beam-lead, hybrid or flip chip technique. Such methods of interconnection generally require more area than if the circuit could be formed directly on the glass substrate, a goal which is highly desirable since it should reduce device size, increase the number of devices which could be processed at one time in a batch run, and increase reliability due to the need to make fewer "off-chip" interconnections. Improved performance and/or precision could also result.
Finally, current SOI techniques do not offer very good film uniformity or crystallinity over the area of an entire chip, let alone over an entire wafer. This greatly reduces yield and makes commercialization of SOI technologies economically impractical for all but the most exotic applications where normal cost considerations do not apply.
In an effort to overcome the foregoing problems, we have worked on new techniques for producing single-crystal thin semiconductor films on an insulating substrate, especially glass, which has electronic properties very similar to that bulk crystalline semiconductor films made of the same materials. In particular, we produced semiconductor-on-insulator structures suitable for subsequent fabrication of high-quality electronic devices thereon such as field effect transistors and bipolar junction transistors. Our earlier work involves electrostatic bonding of a silicon wafer, upon which is epitaxially grown a single-crystal film of any thickness, to an insulating substrate, such as glass, and the subsequent thinning of the bonded wafer to retain only the single-crystal film. An etch stop layer buried under the single-crystal film and doping-sensitive etchants are preferably used to accomplish the thinning of the wafer. A composite mobile ion barrier film, which includes a layer of silicon nitride and is bonded between the epitaxial layer and the glass, is used to prevent tramp alkali from the glass substrate from contaminating the silicon epitaxial layer. The resulting single-crystal SOI structure has been used to fabricate prototype NMOS transistors shown to have channel mobilities of 640 cm.sup.2 /V-sec, with leakage currents less than 10.sup.-14 amps/micron for w/l dimensions of 25 microns by 25 microns. We have also worked with bipolar junction transistors made from the aforementioned single-crystal SOI structure. The details of our earlier work is set forth in two commonly assigned, copending U.S. patent applications, the first of which is Ser. No. 027,717, ; filed Mar. 19, 1987, in the name of L. J. Spangler, and Ser. No. 156,854 filed Feb. 17, 1988, in the name of L. J. Spangler and K. D. Wise, the disclosures of which are hereby incorporated by reference.
In the course of our work disclosed in the aforementioned co-pending U.S. patent applications, we also wondered whether others had tried to bond fully-formed integrated circuits and solid-state devices to an insulating substrate using electrostatic bonding. Our searches revealed the following. U.S. Pat. No. 3,397,278 granted in 1968 to D. I. Pomerantz disclosed the electrostatic bonding of a semiconductor device or monolithic circuit to an insulator plate, such as quartz glass, borosilicate glass, or alumina. This patent also suggested bonding several silicon semiconductor devices to an insulating substrate such as glass while the devices still constitute a part of a single integral slice or wafer. U.S. Pat. No. 3,595,717 issued in 1971 to D. I. Pomerantz teaches the anodic bonding of an insulator member to an etched passivating layer covering a surface of a silicon semiconductor device containing p-n junctions. U.S. Pat. No. 4,121,334 to Wallis teaches the electrostatic bonding of a silicon wafer containing etched cavities and diffused integrated circuits thereon to a glass plate, such as Corning 7740 or 7070 glass, having a coefficient of thermal expansion comparable to that of monocrystalline silicon. However, the silicon wafer is not thinned, and the integrated circuits are diffused on a side of the wafer opposite from the side bonded to the glass substrate.
U.S. Pat. No. 4,426,768 to J. Black et al. teaches the fabrication of a plurality of ultra-thin microminiature pressure sensors by joining two silicon wafers by electrostatic bonding. Prior to bonding, the first wafer is processed to form a plurality of resistor arrays coated with a layer of phosphosilicate glass to protect p-n junctions therebelow from contamination by mobile sodium ions in or on the borosilicate glass that is deposited subsequently in later processing steps. A first layer of aluminum is then deposited between these two glass layers, and appears everywhere in the first wafer except in the regions near the resistor arrays. A second layer of aluminum is provided on the back of the second wafer. The first and second aluminum layers are then connected to a 40 to 50 volt DC supply to electrostatically bond the borosilicate glass on the first layer to the undoped silicon layer of the second wafer. After this bonding step, the composite wafer is then processed to form individual pressure sensors. This patent, however, does not mention Forming active electronic devices or circuits on either the first or second wafers. Instead, the transducers are wire-bonded to external circuits.
In our experiments, we found that the electrostatic bonding of integrated circuitry on a silicon wafer to an insulating substrate wrecks havoc with the active regions of the active electronic devices, such as transistors, of the circuitry. For example, the interface between the single-crystal channel region and insulated gate of a field effect transistor is often unpredictably altered, changing the threshold voltage V.sub.T of the device and rendering device performance unsatisfactory. We suspect that others may have also observed this destructive effect that electrostatic bonding has upon integrated circuits, which would help explain why, out of all the recent articles we have seen concerning ongoing efforts to develop an economical and commercially viable SOI technology, none discuss the electrostatic bonding of pre-formed transistor devices and circuits to an insulating substrate as a technique for forming SOI semiconductor devices. Our efforts to overcome such problems lead to the present invention.
A basic object of the present invention is to overcome the foregoing fundamental problems associated with electrostatically bonding fully-formed integrated circuits and electronic devices to an insulating substrate. Another object of the present invention is to produce a semiconductor-on-insulator circuit structure using pre-formed and pre-tested conventional integrated circuitry from a single-crystal silicon wafer. Another object of the present invention is to from a fully-integrated sensor using at least one pre-formed solid-state electronic device on a single-crystal wafer which has an active region of single-crystal semiconductor material and at least a pre-formed portion of a transducer on the same single-crystal wafer, which is electrostatically bonded to an insulating substrate such as glass.
Yet another object of the present invention is to provide a method of making fully integrated SOI sensors, including at least one transducer and an integrated electronic circuit on glass. Still another object is to provide a technique or mechanism to ensure that active semiconductor devices in a fully-formed microelectronic circuit are not damaged when electrostatically bonded at high voltages to a supporting substrate. One more object of the present invention is to provide an efficient manner of processing SOI devices which utilizes a single processing step to perform two or three important functions, including dielectrically isolating electronic devices and exposing previously prepared bond pads.